Name: Field Programmable Gate Array Trainer
Brand: De Lorenzo
SKU: DL FPGA
Availability: InStock

Home > Field Programmable Gate Array Trainer

Vendor

De Lorenzo

Edquip Product Code

PL-689990

Quality Certification

Warranty

12 months

Student product ratio

1 - 2

Production leadtime

120 days

Content languages

English, French, Italian, Spanish

Taining types

In person

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FPGA (Field Programmable Gate Array) is a type of Integrated Circuit that can be programmed after manufacturing to perform specific logic functions. Unlike fixed-function chips, FPGAs offer incredible flexibility and are widely used in industries like aerospace, telecommunications, automotive, and AI.

What makes FPGA special are:

Reprogrammable Hardware: the logic gates can be reconfigured to suit different tasks.
Parallel Processing: unlike CPUs that execute instructions sequentially, FPGAs can perform many operations simultaneously.
Applications: ideal for real-time applications like Signal processing (e.g., audio, video), Cryptography and secure communications, Robotics and automation, AI acceleration and neural networks, and Prototyping custom chips before mass production.
Customizable Architecture: engineers can tailor the chip’s behaviour using hardware description languages like Verilog or VHDL.

The proposed DL FPGA training kit is one kind of multi-function teaching and development equipment with high configuration and high quality.

It is suitable for EDA (Electronic Design Automation) teaching, course design and graduation design of different college, and also suitable for project development.

The trainer adopts unique double board structure “main board + core board” and all of the I/O pins can be set, so DL FPGA can meet the requirements from simple digital circuit experiment to the complicated one. Adopting the EDA technology, the circuit revise become simple, shorten the development cycle, reduce the chip quantity and system volume, design become more flexible, and enhance the system reliability. The experiment method is updated from traditional hardware overlap joint mode to the software design, simulation debugging circuit system.

The trainer consists of a main module with power supply, with the possibility of choosing one of the two proposed systems:

DL FPGA-ALTERA [with Altera (Intel) FPGA].
DL FPGA-XILINX [with Xilinx (AMD) FPGA].

ALTERA and XILINX are two of the leading names in the FPGA world. Both offer powerful platforms, but they differ in architecture, tools, and performance focus.

DL FPGA-ALTERA

Main board with:

1 x Potentiometer with 0 ÷ 3.3V voltage signal.
8 x LEDs.
4 x 7-segment LEDs.
1 x Buzzer.
8 x Bit switches.
1 x 4x4 keyboard.
1 x IIC series EEPROM (24C04).
1 x 16bit VGA interface.
1 x 1602 liquid crystal interface, together with 1602 screen.
1 x 240x320 TFT colourful liquid crystal interface, together with 240x320 TFT screen.
1 x On board USB-RS232 communication interface.
1 x PS/2 keyboard interface.
1 x SD card interface, together with SD card (4GB).
1 x DS1302 clock interface.
1 x Temperature sensor interface, together with temperature sensor (DS18B20).
1 x Infrared receiving interface, together with Infrared remote control.
1 x AD interface.
1 x DA interface.
1 x USB device interface.
1 x Ethernet interface.
1 x Audio CODEC interface.
8 x Fault simulation.

ALTERA Core Board

Cyclone IV FPGA, chip EP4CE10.
Extend 32Mbit series Flash (M25P32), with enough internal storage for user to do uCOS-II system.
Extend 256Mbit SDRAM chip (MT48LC16), with enough internal storage for user to do SOPC (System-On-a-Programmable-Chip) or NIOS II system.
JTAG configuration mode (combining downloads and debugging).
More than 32 extend user I/Os.

Software & Operating System

Quartus II/SOPC builder/NIOS II/Signal tap II.
Windows 10 64bit and Windows 11 64bit, Professional.

TRANING OBJECTIVES

With this board it is possible to perform experiments on the following subjects:

Logic design:

Half adder/full adder/ 8-bit adder/common adder with carry/vector adder/subtracter/data comparator/eight-way selector/encoder, decoder.
Counter: up counter, down counter, parallel counter.
Two state machines: MOORE machine, MEALY machine.
Three shift registers: serial-in/parallel-out and parallel-in/serial-out, serial-in/serial out, parallel-in/ parallel-out.
Pulse generator.
Memory design experiments: ROM.

Standalone design:

LED control experiment.
Buzzer control experiment.
7-segment LED static display experiment.
7-segment LED dynamic scanning experiment.
Key distinguish experiment.
EEPEOM experiment.
1602 liquid display experiments.
320*240 TFT liquid display experiments.
VGA display experiment.
RS232 communication experiment.
PS2 keyboard experiment.
DS1302 experiment.
Temperature sensor experiment.
Infrared experiment.
AD experiment.
DA experiment.
IP core: FIFO IP core experiment.

DSP design:

Vector multiplier.
FFT.

Embedded design (SOPC):

Audio experiment.
Digital Clock experiment (RTC + Keyboard + TFT LCD)
SD card experiment.
USB communication experiment.
Net communication experiment.

System design:

uCOS II operating system experiment.

Prototyping design:

USB-RS232 Converter ASIC design.

ACCESSORIES

The trainer is supplied with the following elements:

DC5V/2A power adapter,
SD Card,
USB Type A-B cable,
USB-RS232 Converter,
Debugger and downloader,
Cables.

Complete with technical documentation, practical manual and software

DL FPGA-XILINX

TECHNICAL FEATURES

Main board with:

1 x Potentiometer with 0 ÷ 3.3V voltage signal.
8 x LEDs.
4 x 7-segment LEDs.
1 x Buzzer.
8 x Bit switches.
1 x 4x4 keyboard.
1 x IIC series EEPROM (24C04).
1 x 16bit VGA interface.
1 x 1602 liquid crystal interface, together with 1602 screen.
1 x 240x320 TFT colourful liquid crystal interface, together with 240x320 TFT screen.
1 x On board USB-RS232 communication interface.
1 x PS/2 keyboard interface.
1 x SD card interface, together with SD card (4GB).
1 x DS1302 clock interface.
1 x Temperature sensor interface, together with temperature sensor (DS18B20).
1 x Infrared receiving interface, together with Infrared remote control.
1 x AD interface.
1 x DA interface.
1 x USB device interface.
1 x Ethernet interface.
1 x Audio CODEC interface.
8 x Fault simulation.

XILINX Core Board

Sparten VI FPGA, chip XC6SLX9.
Extend 32Mbit series Flash (M25P32), with enough internal storage for user to do uCOS-II system.
Extend 256Mbit SDRAM chip (MT48LC16), with enough internal storage for user to do SOPC (System-On-a-Programmable-Chip) or NIOS II system.
JTAG configuration mode (combining downloads and debugging).
More than 32 extend user I/Os.

Software & Operating System

ISE/EDK/SDK/ChipScope.
Windows 10 64bit and Windows 11 64bit, Professional.

TRANING OBJECTIVES

With this board it is possible to perform experiments on the following subjects:

Logic design:

Half adder/full adder/ 8-bit adder/common adder with carry/vector adder/subtracter/data comparator/eight-way selector/encoder, decoder.
Counter: up counter, down counter, parallel counter.
Two state machines: MOORE machine, MEALY machine.
Three shift registers: serial-in/parallel-out and parallel-in/serial-out, serial-in/serial out, parallel-in/ parallel-out.
Pulse generator.
Memory design experiments: ROM.